UCSB Computer Science student Weilong Cui and Professor Tim Sherwood had their work “Architectural Risk” picked for this prestigious IEEE Micro "Top Pick" award for 2018. This year 12 papers we selected by a combination of industry experts and faculty from across all of the top computer architecture conferences. Their work explores the relationship between the economic notion of "risk" and the standard performance optimization techniques computer system designers have relied on for decades. Designing a system in an era of rapidly evolving application behaviors and significant technology shifts involve taking on risk that a design will fail to meet its performance goals. While risk assessment and management are expected in both business and investment, these aspects are typically treated as independent to questions of performance and efficiency in architecture analysis. 

As hardware and software characteristics become more uncertain (due to radical changes happening across both circuit technology and computing applications), they demonstrate that the resulting performance distributions quickly grow beyond our ability to reason about with intuition alone. They further show that knowledge of the performance distribution can be used to significantly improve both the average case performance and minimize the risk of under-performance. They present a new automated framework can be used to quantify the areas where trade-offs between expected performance and the "tail" of performance are most acute. An end to goal is to create a "portfolio" of machines that, when taken together, are far more robust to changes in the underlying technology. The paper will appear in the May-June 2018 award edition of IEEE Micro.