Peter Cappello
Professor Emeritus
He/Him/His
cappello@cs.ucsb.edu
2107 Harold Frank Hall
Personal Website
Education
Ph.D. Computer Science, Princeton University
M.S. Computer Science, UC Berkeley
B.S. Mathematics, Pennsylvania State University
B.S. Computer Science, Pennsylvania State University
Campus Affiliations
College of Creative Studies
External Publications
GoogleScholar
Awards
NSF Research Initiation Award
Patent award: "Systolic super summation device," Peter Cappello on behalf of the University of California and the National Science Foundation, and Willard L. Miranker on behalf of the IBM Corporation.
European patent 87101193.8-, Feb. 10, 1987.
US patent 4,751,665, June 14, 1988.
Research Areas
Operating Systems and Distributed Systems
Bio

He is a senior member of the IEEE, and a member of the IEEE Computer Society, the IEEE Signal Processing Society, the ACM, and the Advisory Board of the IEEE Signal Processing Society's Technical Committee (TC) on Design & Implementation of Signal Processing Systems (previously the TC on VLSI), of which he served as founding Chair.

He chaired the 1984 IEEE Workshop on VLSI Signal Processing and co-edited VLSI Signal Processing (IEEE Press).  He was Program Co-Chair of the 1994 Int. Conf. on Application Specific Array Processors (ASAP'94) and Conference Co-Chair for ASAP'95, is a past Associate Editor of the IEEE Trans. on Acoustics, Speech, & Signal Processing, and is on the editorial board of the J. Signal Processing Systems.

Research

He has investigated multi-processor scheduling, systolic arrays, and the relationship between algorithms and architectures for parallel processing.  Via Javelin, CX, and, the JICOS project, he is investigating distributed cloud computing.  Recently, he has leveraged the Jicos project in the development of jpregel for developing and executing distributed graph algorithms in clouds.  He also is interested in self-directed learning. He has published journal articles on Java-centric parallel and distributed computing, optimal multiprocessor schedules for fundamental algorithms, a programming language for systolic algorithms, parallel algorithms for scientific computations, formal manipulation of systolic algorithms, integer multiplication, bit-level systolic algorithms, special-purpose architectures for digital signal processing, and computer-aided design of digital filter chips.