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Each year a committee of industry experts and faculty chooses 10 papers
from the top computer architecture conferences to highlight in the
annual “Top Picks” issue of IEEE Micro. This year UCSB
Computer Engineering student Jonathan Valamehr, Computer Science
and Engineering Professor Tim Sherwood, and thier collaborators from
Microsoft, had their work “Inspection Resistant Memory Architectures”
selected for this prestigious publication.

The ability to safely keep a secret in memory is central to the vast
majority of security schemes, but storing and erasing these secrets is a
difficult problem in the face of an attacker who can obtain unrestricted
physical access to the underlying hardware. Depending on the memory
technology, the very act of storing a 1 instead of a 0 can have physical
side effects measurable even after the power has been cut. These effects
cannot be hidden easily, and if the secret stored on chip is of
sufficient value, an attacker may go to extraordinary means to learn
even a few bits of that information. Solving this problem requires a
new class of architectures that measurably increase
the difficulty of physical analysis. Jonathan and his collaborators take
a first step towards this goal by focusing on one of the backbones of
any hardware system: on-chip memory. They examine the relationship
between security, area, and efficiency in these architectures, and
quantitatively examine the resulting systems through cryptographic
analysis and microarchitectural impact. In the end, they are able to
find an efficient scheme in which, even if an adversary is able to
inspect the value of a stored bit with a probabilistic error of only 5%,
the system will be able to prevent that adversary from learning any
information about the original un-coded bits with 99.9999999999%
probability. The paper will appear in the February 2013 award edition
of IEEE Micro.

If you are interested you can read more about this group and their
activities on Professor Sherwood’s homepage.