Managing uncertainty and risk is an increasingly important aspect of computer architecture as we navigate the new dark waters exposed by changes in fabrication, design constraints, and programming models. An uncertainty-aware approach is essential when we design computer architectures and systems for the future, as variations in technology alone has been demonstrated to have the potential of eliminating the performance gain of an entire CMOS generation. A clear understanding and rigorous quantification of uncertainties in architecture designs, as well as the risks that come along, is a critical first step. To achieve such a goal in a tremendous space of designs, we need new systematic supports across the design stack from high level analytical analysis when evaluating design decisions in the early stage to cycle-accurate detailed simulations when projecting actual system performance.
In this talk, I will present my phd work en route to build a new uncertainty and risk aware architecture design process. I'll first demonstrate how even a very high level definition and understanding of such concepts of uncertainties and risks can expose a new trade-off space between average-case performance and the amount of uncertainty/risk a design is exposed to. The framework is then generalized to a new modeling language that systematically support such analysis through a combination of symbolic execution, graph transformation and compiler optimizations. I'll then take the exploration down to the most common practice of architecture studies: cycle-accurate simulations. There a new way of quantifying uncertainty and risk while keeping the computational taxing at bay is proposed through the adaptation of generalized polynomial-chaos theories to build accurate surrogate models. Finally, I'll peak into the future and envision what needs to be researched before quantifying uncertainties and risks become an essential and well-supported practice of future architecture design.