Two Scalable Core Architectures for Power-Constrained CMPs

Tuesday, October 11, 2011 - 11:45am


Monday, October 31, 2011
3:30 – 4:30 PM
Room 1132 Harold Frank Hall

HOST: Tim Sherwood

SPEAKER: David A. Wood
University of Wisconsin, Madison

Title: Two Scalable Core Architectures for Power-Constrained CMPs


Chip Multiprocessors (CMPs) are now commodity hardware, but
commoditization of parallel software remains elusive. In the near term,
the current trend of increased core-per-socket count will continue,
despite a lack of parallel software. Future CMPs must deliver
thread-level parallelism when software provides threads to run, but must
also continue to deliver high single-thread performance–via
instruction-level and memory-level parallelism–to mitigate sequential
bottlenecks and/or to guarantee service-level agreements. However, power
limitations will prevent conventional cores from exploiting both

The Wisconsin Multifacet project has recently developed two alternative
scaleable core architectures, which can scale their execution logic up
to run single threads fast, or down to run multiple threads within a
fixed power budget. WiDGET (Wisconsin Decoupled Grid Execution Tiles)
decouples thread context management from a sea of simple execution
units. WiDGET’s decoupled design provides flexibility to alter
resource allocation for a particular power-performance target while
turning off unallocated resources. Forwardflow dynamically builds an
explicit internal dataflow representation from a conventional
instruction set architecture, using forward dependence pointers to guide
instruction wakeup, selection, and issue. Forwardflow’s backend is
organized into discrete units that can be individually (de-)activated,
allowing each core’s performance to be scaled by system software at
the architectural level.


Prof. David A. Wood is a Professor in the Computer Sciences Department
at the University of Wisconsin, Madison and has a joint appointment in
Electrical and Computer Engineering. Dr. Wood was named an ACM Fellow
(2005) and IEEE Fellow (2004), received the University of Wisconsin’s
H.I. Romnes Faculty Fellowship (1999), received the National Science
Foundation’s Presidential Young Investigator award (1991), and earned
his Ph.D. in Computer Sciences from the University of California,
Berkeley (1990). Dr. Wood is Chair of ACM Special Interest Group on
Computer Architecture (SIGARCH), Area Editor (Computer Systems) of ACM
Transactions on Modeling and Computer Simulation, is Associate Editor of
ACM Transactions on Architecture and Compiler Optimization, served as
Program Committee Chairman of ASPLOS-X (2002), and has served on
numerous program committees. Dr. Wood is an ACM Fellow, an IEEE Fellow,
and a member of the IEEE Computer Society. Dr. Wood has published over
70 technical papers and is an inventor on twelve U.S. and International
patents. Dr. Wood co-leads the Wisconsin Multifacet project with Prof.
Mark Hill (URL which is exploring
techniques for improving the availability, designability,
programmability, and performance of commercial multiprocessor and chip
multiprocessor servers.