Architectures for Streaming Introspection

Date: 
Wednesday, October 3, 2007 - 3:31pm


SPEAKER: TIM SHERWOOD, UCSB, Computer Science
DATE: Wednesday, October 3, 2007
TIME: 3:30 – 4:30 p.m.
PLACE: Computer Science Conference Room, Harold Frank Hall Room 1132

ABSTRACT:

Modern computer systems are called on to deal with billions of events every second, whether they are instructions executed, memory locations accessed, or packets forwarded. Sifting through these data streams has many applications, from helping to identify attackers (e.g. intrusion detection), enabling higher performance (e.g. profiling), or assisting in debugging and reliability (e.g. introspection). As our applications and software continue to grow in complexity it is worth considering a redesigned computing device that supports online high-throughput deep event analysis as a first class citizen — everywhere from the circuits to the software.

Extracting, processing, and acting upon event streams at such a high rate of speed requires a rethinking of both the computer architecture and its underlying assumptions. In this talk I will provide an overview of the work being done in our UCSB lab, towards this goal. To ground our discussion in a concrete example, I will concentrate on virtually-pipelined memory — an architectural technique that efficiently supports high-bandwidth, uniform latency memory accesses, and high-confidence throughput even under adversarial conditions. The presented approach allows designers to effectively decouple the analysis of their algorithms and data structures from the underlying hardware details such as memory buses and banks, yet outperforms prior techniques which have been carefully hand-crafted to work for only specific access
patterns.

BIOGRAPHY:

Tim Sherwood is an Assistant Professor in the department of Computer
Science at UC Santa Barbara. His research is in the area of computer
architecture, specifically in the development of novel high throughput
methods by which systems can be monitored and analyzed. Professor
Sherwood has received the IEEE Micro Top Pick Award for novel
contributions significant to industry on 3 different occasions, and in
2005 received the NSF CAREER award. His work on Program Phase Analysis,
(a technique for reasoning about and predicting the behavior of programs
over time) has been cited over 350 times and is now used by Intel, HP,
and other industry partners to guide the design of their largest
microprocessors. Prior to joining UCSB in 2003, he received his B.S in
Computer Science and Engineering from UC Davis, and his Ph.D. in the
same from UC San Diego.