“Life After Dennard and How I Learned to Love the Picojoule”

Wednesday, January 18, 2012 - 3:49pm


Monday, February 6, 2012
2:00 – 3:00PM
Computer Science Conference Room, Harold Frank Hall, Rm. 1132

SPEAKER: Stephen Keckler
Professor, CS and ECE, University of Texas at Austin and Director of Architecture Research, NVIDIA

TITLE: “Life After Dennard and How I Learned to Love the Picojoule”

Life in the time of Dennard scaling was relatively easy for architects and the computer industry. Every process generation delivered twice as many transistors to a chip that could run at a 1.4 times faster clock rate and consume the same power as the previous generation. General purpose processors spent this bounty on deep pipelining for high clock rates, extreme out-of-order execution to mine instruction-level parallelism, and large on-chip caches. In today’s post-Dennard scaling world that no longer benefits from voltage scaling, each generation of process technology doubles chip transistor count but requires 40% more power at the same clock rate as the previous generation. In this era, every computing device is energy or power limited and energy efficiency is equivalent to performance. This talk will describe the challenges facing computer architectures, ranging from mobile devices to high-performance computers. Using examples from contemporary architectures, it will then discuss strategies for creating energy-efficient computers, including extreme energy-efficient microarchitectures, parallelism, data locality, and specialization. The talk will conclude with a set of challenges for the architecture research community and discuss why this era is providing a renaissance of opportunity for innovative computer architectures.

Steve Keckler is the Director of Architecture Research at NVIDIA and Professor of both Computer Science and Electrical and Computer Engineering at the University of Texas at Austin. His research team at UT-Austin developed scalable parallel processor and memory system architectures, including non-uniform cache architectures; explicit data graph execution processors; and micro-interconnection networks to implement distributed processor protocols. At NVIDIA, Dr. Keckler focuses on parallel, energy-efficient architectures that span mobile through supercomputing platforms. He is a Fellow of the ACM, a Fellow of the IEEE, an Alfred P. Sloan Research Fellow, and a recipient of the ACM Grace Murray Hopper award, the President’s Associates Teaching Excellence Award at UT-Austin, and the Edith and Peter O’Donnell award for Engineering. He earned a BS in Electrical Engineering from Stanford University and an MS and a Ph.D. in Computer Science from the Massachusetts Institute of Technology.