Tiwari et. al. win IEEE Micro Top Pick Award for Technique to Create Secure Computer Hardware

December 22, 2009

Each year a committee of industry experts and faculty chooses 10 papers from
the top computer architecture conferences to highlight in the annual “Top
Picks” issue of IEEE Micro. This year UCSB Computer Science students Mohit
Tiwari, Xun Li, Hassan Wassel, Bita Mazloom, and Shashi Mysore along with
their advisors Fred Chong and Tim Sherwood had their work on
Tracking Information Flow at the Gate-Level for Secure Architectures

selected for this prestigious publication.

Systems responsible for controlling aircraft, protecting the master secret
keys for a bank, or regulating access to extremely sensitive commercial or
military information, all demand a level of assurance far beyond the norm.
Creating these systems today is an incredibly expensive operation both in
terms of time and money costing upwards of $10,000 per line of code. The
authors propose a new method for constructing and analyzing computer
hardware architectures capable of tracking all information flow within the
machine for security purposes. Starting from a simple NAND gate, they
describe how to to create more complex structures including muxes, control,
registers, and finally a small microprocessor, which they then implemented
and tested on an FPGA.

If you are interested you can read more about this group and their
activities on the UCSB Computer Architecture Group Webpage.