Welcome to the website of the UCSB Computer Architecture Lab

Computer Architecture research will define with the way that future generations of computing machines will be organized and designed. The UCSB ArchLab, directed by Professors Fred Chong, Diana Franklin, and Tim Sherwood, aims to push the frontiers of computer architecture by taking an interdisciplinary and cross-cutting approach. Computer Architecture is not an island, but rather it sits between algorithms, operating systems, compilers, circuits, networks, and security; by looking at computer architecture through the eyes of it's application we can enact the biggest change. This is the basic philosophy of our lab.

Introspective Computing

Even today, software bugs are so damaging and widespread that they cost the U.S. economy alone an estimated $59.5 billion annually (more than half a percent of the US GNP). As our applications and software continue to grow in complexity, it is worth considering a processor with built-in support for introspection -- everywhere from the circuits to the software. Such a design could enable systems that monitor themselves for defects, that catch security violations as they occur, and optimize themselves over time. My lab has been been considering the use of novel technologies, such as 3D-Integration, to add introspection hardware in the last stages of processor fabrication. With a small amount of hardware support, we can help guide program profiling, direct processor reconfiguration, and enable new methods that track events both spatially and temporally. Portions of this work were selected by IEEE Micro as some of the top picks of 2004 (on phases) and 2006 (on 3d introspection)

Quantum Computing Architectures

Together with Isaac Chuang (MIT) and John Kubiatowicz (Berkeley), Prof. Chong founded the Quantum Architecture Research Center (QARC), which was supported by a 5-year $3M grant from the DARPA Quantum Information Science and Technology Program. For its efforts in prototyping quantum computers, QARC was awarded the 2002 DARPATech Significant Technical Achievement Award, for the most significant DARPA-supported technical achievement in two years. Our work is the only project of its kind, designing scalable quantum computing architectures which plot the course for other projects working on quantum devices and fabrication technology. Our work is now part of the CNSI Center for Spintronics and Quantum Computation.

Processor Support for System Security

Prof. Chong's work includes the design of processors which enhance system security. These designs include Minos, a tagged microarchitecture which implements Biba's low-water-mark policy, but focuses on data used for control decisions. We have implemented Minos on a Pentium-based emulator and deployed Minos-enhanced Linux and Windows systems on the Internet. These systems detect and prevent dozens of known and unknown attacks per day. Extensive stress tests show that Minos is a stable, robust, and securable system. Related work exploits Minos to suspend system state at attack time to automatically analyze and inoculate non-Minos systems to these attacks through a system called DACODA.

Next Generation DSP Architectures

Recent work has focused on the design of power-efficient, next-generation architectures for embedded microprocessors. Our architecture, called Synchroscalar, uses a small set of discrete voltages and frequencies, exploiting spatial flexibility to partition tasks on to different pieces of hardware rather than varying the voltage of the same piece of hardware.

Network and Security Processing

A primary focus of Prof. Sherwood's research is designing new computer architectures specifically to be embedded into the network. Applications in this domain are throughput-driven, irregular, and bounded by the need for worst-case performance. These characteristics are not well supported by cache-heavy latency-intolerant traditional designs. The architecture we are developing takes advantage of many small, wide word, on-chip memories to rapidly traverse the large graph structures common to many security applications. In addition to the novel architecture work here, we also provide a set of memory models for modeling Ternary CAM (TCAM) power and delay tool that is simple to use, accurate and validated. It can help networking people and architects to explore various SRAM-TCAM hybrid algorithms and quantify the overhead and improvement.

Reconfigurable Security

From Bluetooth transceivers to the NASA Mars Rover, reconfigurable circuits have become one of the mainstays of embedded design. Combining the high computational performance of specialized circuits with the re-programmability of software, these devices are quickly becoming ubiquitous - unfortunately this hardware malleability can be twisted to disrupt critical operations, snoop on supposedly secure channels, or even to physically melt a device. The goal of the RCsec project is to enable a new class of systems that are both reconfigurable and secure. The effort concentrates on three main areas in order to achieve these goals: enforcing logic-level separation, advanced memory protection, and dynamic policy management.

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