Due to the large amount of power that data centers and HPC systems consume, energy-efficiency improvements are critical for sustainable performance scaling of these systems. Memories pose a looming power bottleneck for future data centers and HPCs due to both application-level and micro-architectural trends. For example, in high memory capacity server systems, memory can occupy up to 40% of server power budget; similarly, for future exascale supercomputers, memory power has been projected to occupy 40-70% of the power budget per computing node. To tackle the memory power problem, I propose common-case optimized memory design, which reduces the energy overheads of common-case memory accesses (e.g., fault free accesses) at the expense of increasing the energy overheads for uncommon case accesses (e.g., accesses to faulty locations). Since common-case accesses are much more frequent than uncommon-case accesses, this tradeoff significantly reduces overall memory energy overheads. In the talk, I will describe common-case optimized memory architectures both for off-chip main memory and on-chip cache memories; the proposed common-case optimized off-chip main memory architecture improves memory energy efficiency by 30-50% while the proposed common-case optimized on-chip main memory architecture improves processor-core-wide energy efficiency by 16%.
Xun Jian is a PhD candidate in the Electrical and Computer Engineering department at the University of Illinois at Urbana-Champaign. He works in the area of computer architecture with special focus on server architectures for improving the future scaling of data centers and HPC systems. His graduate work has been recognized by several best paper awards (SRC TECHCON 2014, IEEE CAL 2013, SRC TECHCON 2015) and has led to technology transfer to industry (patent rights acquired by Empire Technology Development LLC). He was one of the invitees to the Heidelberg Laureate Forum and is a recipient of the M. E. Van Valkenburg Graduate Research Award, the highest award in ECE Illinois to recognize graduate research excellence in the areas of circuits, systems, or computers.