ArchLab paper selected for 2013 IEEE Micro Top Picks

July 1, 2014

Each year a committee of industry experts and faculty chooses 10 papers from the top conferences to highlight in the annual "Top Picks" issue of IEEE Micro — and UCSB yet again has a paper on the list. This year the paper is titled "SurfNoC: A Low Latency and Provably Non-Interfering Approach to Secure Networks-On-Chip" and represents a collaboration between UC Santa Barbara, UC San Diego, and the Naval Postgraduate School.

In high assurance systems it is common practice to break the system into a set of domains which are to be kept separate. These domains should have no-effect on one another. For example, the Mars curiosity rover runs  on a RAD750 processor, a single-core radiation-hardened version of the Power architecture with a special purpose separation kernel. The kernel partitions the tasks such as guidance, navigation and the various science packages from one another to help prevent cascading failures.

In their paper, the UCSB authors introduce an on-chip network that significantly reduces the latency incurred by temporal partitioning. By carefully scheduling the network into waves that flow across the interconnect, data with different labels carried by these wave are strictly non-interfering while avoiding the significant overheads associated with cycle-by-cycle time multiplexing.  They describe the scheduling policy and router architecture changes required, and evaluate the information-flow security of a synthesizable implementation through gate-level information flow analysis. When comparing their approach for varying numbers of labels, network sizes, and queue sizes, they find that in many cases SurfNoC can reduce the latency overhead of implementing cycle level non-interference by up to 85%.

The work was led by Ph.D. student Hassan Wassel (now at Google) and advised by Prof. Tim Sherwood. The IEEE Micro Top Picks from 2013 article is available here and the original paper is available here.